1. Field of the Invention
The present invention relates to a signal detecting circuit for converting a differential signal into a binary signal.
2 Description of the Related Art
In recent years, a high-speed transfer is demanded in data transfer to a HDD drive or the like. Conventionally, a conventional parallel transfer method has been employed. In the conventional parallel transfer method, data are transferred in parallel by using the large number of signal lines. Therefore, when the data transfer speed is made higher, synchronization has become difficult between a large number of signal lines and has become close to its limit. For this reason, a differential serial transfer method begins to be spread to allow the high speed data transfer. In the differential serial transfer method, two transmission paths as one set are used and a data is transferred as a voltage difference between the two transmission paths. Thus, the differential serial transfer method is suitable for the higher speed transfer.
On the other hand, in association with the higher speed transfer, a detection time becomes short and the amplitude of a signal is decreased, which requires a signal detecting circuit having a higher precision. A conventional example of the signal detecting circuit in such a situation is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-55968).
FIG. 1 is a circuit diagram showing the configuration of the conventional example. In this conventional example, the signal detecting circuit includes comparing circuits CMP1 and CMP2, an exclusive-OR circuit EOR1, and resistances R1, R2 and R3. The resistances R1, R2 and R3 set reference voltages serving as threshold levels of the comparing circuits. At this time, the threshold level of the comparing circuit CMP2 is set to be lower than the threshold level of the comparing circuit CMP1. The comparing circuits CMP1 and CMP2 have different threshold levels, and output comparison resultant signal CMP1out and CMP2out from an input signal Sin. The exclusive-OR circuit EOR1 outputs an exclusive-OR result as a signal SIv between the comparison resultant signals CMP1out and CMP2out.
When the amplitude of the input signal Sin is sufficiently larger than the reference voltages of the comparing circuits CMP1 and CMP2, the exclusive-OR result between the signals CMP1out and CMP2out is “0”. Also, when the amplitude of the input signal Sin is equal to or less than the threshold level of the comparing circuit CMP1, the output of the comparing circuit CMP1 is zero. However, the comparing circuit CMP2 detects the input signal, since having the lower threshold level than that of the comparing circuit CMP1. Thus, the exclusive-OR result between the signals CMP1out and CMP2out is “1”. In this way, the amplitude of the signal can be detected from the output SIv of the exclusive-OR circuit EOR1 by the setting of the threshold levels of the comparing circuits CMP1 and CMP2.
FIG. 2 shows a circuit diagram of a second conventional example where the input signal of the above-mentioned conventional example is replaced by the differential input signal.
This conventional circuit includes differential comparing circuit CMP3, CMP4, CMP5 and CMP6, and a differential exclusive-OR circuit EOR2. The differential comparing circuit CMP3 includes resistances R5 and R6, N-channel transistors Mn1 and Mn2 and a constant current source Ib3. The differential comparing circuit CMP3 receives a differential input signal Sin of a positive phase input signal SinP and an inversion phase input signal SinN, and outputs differential resultant signals CMP3outP and CMP3outN. The differential comparing circuit CMP4 includes N-channel transistors Mn3 and Mn4 and a constant current source Ib4. The differential comparing circuit CMP4 gives an offset voltage to the differential comparing circuit CMP3. The differential comparing circuit CMP5 includes resistances R7 and R8, N-channel transistors Mn5 and Mn6 and a constant current source Ib5. The differential comparing circuit CMP5 receives the differential input signal Sin of the positive phase input signal SinP and the inversion phase input signal SinN, and outputs differential resultant signals CMP5outP and CMP5outN. The differential comparing circuit CMP6 includes N-channel transistors Mn7 and Mn8 and a constant current source Ib6. The differential comparing circuit CMP6 gives the offset voltage to the differential comparing circuit CMP5. The differential exclusive-OR circuit EOR2 connected to the outputs of the differential comparing circuit CMP3 and CMP5, and a constant current source Ib2, a resistance R4 and a reference voltage V1 set an offset voltage (=R4H−R4L).
Next, an operation of the second conventional example will be described below by using the operation waveforms shown in FIGS. 3A to 3D. When the amplitudes of the positive phase input signal SinP and inversion phase input signal SinN are small, the positive phase output signal CMP3outP from the differential comparing circuit CMP3 is a signal where an offset is given to the positive phase input signal SinP based on a reference voltage R4L supplied to the differential comparing circuit CMP4, as shown in FIG. 3B. The inversion phase output signal CMP3outN from the differential comparing circuit CMP3 is a signal where an offset is given to the inversion phase input signal SinN based on a reference voltage level R4H supplied to the differential comparing circuit CMP4, as shown in FIG. 3B. These reference voltages R4H and R4L have the offset voltage determined based on the constant current source Ib2 and the resistance R4. Similarly, the positive phase output signal CMP5outP from the differential comparing circuit CMP5 is a signal where an offset is given to the positive phase input signal SinP based on the reference voltage R4H supplied to the differential comparing circuit CMP6, as shown in FIG. 3C. The inversion phase output signal CMP5outN from the differential comparing circuit CMP5 is a signal where an offset is given to the inversion phase input signal SinN based on the reference voltage level R4L supplied to the differential comparing circuit CMP6, as shown in FIG. 3C. In the differential exclusive-OR circuit EOR2, the signals CMP3outP and CMP3outN are compared, and the signals CMP3outP and CMP3outN indicate “1” when the signal CMP3outP is equal to or larger than the first signal CMP3outN, and the signals CMP3outP and MP3outN indicate “0” when the signal CMP3outP is smaller than the signal CMP3outN. Also, the signals CMP5outN and CMP5outP are compared, and the signals CMP5outN and CMP5outP indicate “0” when the signal CMP5outN is equal to or larger than the signal CMP5outP and the signals CMP5outN and CMP5outP indicate “1” when the signal CMP5outN is smaller than the signal CMP5outP. The signal SoutP is outputted as an exclusive-OR result between the first and second signals. The signal SoutN is outputted as an inverted signal of the signal SoutP.
On the other hand, when the amplitudes of the positive phase input signal SinP and inversion phase input signal SinN are large, the signal CMP3outN becomes equal to or larger than the signal CMP3outP at a clock cycle, as shown in FIG. 3B. At this time, the signals CMP3outP and CMP3outN indicate “0”. Also, the signal CMP5outP becomes equal to or larger than the signal CMP5outN at a clock cycle, as shown in FIG. 3c. At this time, the signals CMP5outN and CMP5outP indicate “1”.
As a result, the signal SoutP is in the high level when the amplitudes of the signals SinP and SinN are small and is in the low level when the amplitudes of the signals SinP and SinN are large. Thus, the fact that the differential input signal Sin is supplied is detected.
By the way, in order to design the signal detecting circuit having a higher precision, it is necessary to consider the manufacturing deviation of resistances, capacitors and transistors of the circuit. In order to reduce the influence of the manufacturing deviation, there are a method of enlarging the size of the transistor, and a method of adding a circuit for correcting the manufacturing deviations. However, the increase in a layout area or the increase in a current consumption is caused even in both of the methods. In addition, the increase in the size of the transistor and the addition of the manufacturing deviation correcting circuit bring about the increase in the wiring capacitance and gate capacitance and also hinder the correspondence to a higher speed signal.
In case of the second conventional example, the constant current source Ib2 and the resistance R4 receive the influence of the manufacturing deviation. An error and parasitic capacitance of the differential comparing circuits CMP4 and CMP5 due to the manufacturing deviation hinder the precision improvement and the speed improvement.